White Papers

The Unified Network - Performance; Scalability; Manageability
April 2007 - iVivity, Inc.  
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SUMMARY: The growing reliance on digital information with its demand for voice, video and data is forcing companies to deal with multiple technically dissimilar networks. These networks provide the necessary performance, security and reliability to meet today's insatiable demand for all these traffic types. Local Area Networks (LANs), using Ethernet, connect multiple computers together for the exchange of basic information, like email and files. For the more demanding environments,like storage, a special purpose network, such as Fibre Channel, is deployed requiring a different set of equipment and dedicated personnel with advanced skill sets to design and maintain. If the compute environment requires extreme performance with low latency, a High Performance solution such as clustering based on Infiniband or a proprietary solution is implemented. These systems create levels of complexity that push management costs as high as 8 times the original hardware/software purchased cost. A major part of the savings is using the same network technology across all the different networks, that can be differentiated by logical rather than physical attributes 10G Ethernet, along with the emerging 10GBaseT copper PHY technology, provides the most logical base network for all three functions. However, in order to provide low latency and support for different applications, 10G Ethernet must operate at wire speed regardless of packet size, including small packets (e.g., 64 bytes). It must also provide a logical delineation between different applications running on the same physical medium.

Achieving Software Load Balance On Systems Using Message-based Interconnect Protocol
Jan 23 2007 - Marc Karasek and Rafiq Batcha - iVivity, Inc.
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SUMMARY: The paradigm for using the PCI bus in a co-processor model in FPGA or ASIC implementations has been one of extending the core system's functionality through addition of peripherals on the PCI bus. In a typical application, the core system has a central CPU (Host), with a companion chip that provides some level of connectivity and functionality to the outside world. This model isolates the host system (CPU + companion chips) from the added peripheral (HBA). The software in this model also compartmentalizes what applications and tasks execute on the system as opposed to the added peripheral. The limitation is that this does not allow for moving functionality from the system to the added peripheral, or vice-versa, easily. From a system perspective, this is a very rigid system with little or no room for optimization. Any host-peripheral interface that allows specific software functionality to be flexibly deployed within the system would lead to better overall system performance. This would allow the application developer to determine what the optimum software load balance between the host and the peripheral(s) in the system is. One such model would be to extend a messaging mechanism over PCI from the peripheral to the system that allows the peripheral to appear as an extension of the system. Using this model software blocks in the host could be moved to run on the peripheral or vice-versa with minimal effort. In addition, this would also lead to significantly improved I/O performance between the host and peripheral. In effect, the peripheral no longer exists as an appendage to the system but is an integral part of it. This paper then outlines the workings of one such host-peripheral messaging implementation on iVivity's iDiSX family of application I/O acceleration processors.